Body Controlled Double Channel Transistor and Circuits Comprising the Same

ABSTRACT

By forming a non-oxidizable liner in an isolation trench and selectively modifying the liner within the isolation trench, the stress characteristics of the isolation trench may be adjusted. In one embodiment, a high compressive stress may be obtained by treating the liner with an ion bombardment and subsequently exposing the device to an oxidizing ambient at elevated temperatures, thereby incorporating silicon dioxide into the non-oxidizable material. Hence, an increased compressive stress may be generated within the non-oxidizable layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Generally, the present invention relates to the formation of integratedcircuits, and, more particularly, to the formation of isolation trenchesthat may be used as strain-inducing sources of transistors havingstrained channel regions to enhance charge carrier mobility in thechannel region of a MOS transistor.

2. Description of the Related Art

The fabrication of integrated circuits requires the formation of a largenumber of circuit elements on a given chip area according to a specifiedcircuit layout. Generally, a plurality of process technologies arecurrently practiced, wherein, for complex circuitry, such asmicroprocessors, storage chips and the like, CMOS technology iscurrently the most promising approach due to the superiorcharacteristics in view of operating speed and/or power consumptionand/or cost efficiency. During the fabrication of complex integratedcircuits using CMOS technology, millions of transistors, i.e., N-channeltransistors and P-channel transistors, are formed on a substrateincluding a crystalline semiconductor layer. A MOS transistor,irrespective of whether an N-channel transistor or a P-channeltransistor is considered, comprises so-called PN junctions that areformed by an interface of highly doped drain and source regions with aninversely doped channel region disposed between the drain region and thesource region.

The conductivity of the channel region, i.e., the drive currentcapability of the conductive channel, is controlled by a gate electrodeformed above the channel region and separated therefrom by a thininsulating layer. The conductivity of the channel region upon formationof a conductive channel, due to the application of an appropriatecontrol voltage to the gate electrode, depends on the dopantconcentration, the mobility of the majority charge carriers, and, for agiven extension of the channel region in the transistor width direction,on the distance between the source and drain regions, which is alsoreferred to as channel length. Hence, in combination with the capabilityof rapidly creating a conductive channel below the insulating layer uponapplication of the control voltage to the gate electrode, the overallconductivity of the channel region substantially determines theperformance of the MOS transistors. Thus, the reduction of the channellength, and associated therewith the reduction of the channelresistivity, renders the channel length a dominant design criterion foraccomplishing an increase in the operating speed of the integratedcircuits.

The continuing shrinkage of the transistor dimensions, however, involvesa plurality of issues associated therewith that have to be addressed soas to not unduly offset the advantages obtained by steadily decreasingthe channel length of MOS transistors. One major problem in this respectis the development of enhanced photolithography and etch strategies toreliably and reproducibly create circuit elements of criticaldimensions, such as the gate electrode of the transistors, for a newdevice generation. Moreover, highly sophisticated dopant profiles, inthe vertical direction as well as in the lateral direction, are requiredin the drain and source regions to provide low sheet and contactresistivity in combination with a desired channel controllability. Inaddition, the vertical location of the PN junctions with respect to thegate insulation layer also represents a critical design criterion inview of leakage current control. Hence, reducing the channel length mayusually also require reducing the depth of the drain and source regionswith respect to the interface formed by the gate insulation layer andthe channel region, thereby requiring sophisticated implantationtechniques. According to other approaches, epitaxially grown regions areformed with a specified offset to the gate electrode, which are referredto as raised drain and source regions, to provide increased conductivityof the raised drain and source regions, while at the same timemaintaining a shallow PN junction with respect to the gate insulationlayer.

Since the continuous size reduction of the critical dimensions, i.e.,the gate length of the transistors, necessitates the adaptation andpossibly the new development of highly complex process techniquesconcerning the above-identified process steps, it has been proposed toalso enhance the channel conductivity of the transistor elements byincreasing the charge carrier mobility in the channel region for a givenchannel length, thereby offering the potential for achieving aperformance improvement that is comparable with the advance to a futuretechnology node while avoiding or at least postponing many of the aboveprocess adaptations associated with device scaling. One efficientmechanism for increasing the charge carrier mobility is the modificationof the lattice structure in the channel region, for instance by creatingtensile or compressive stress in the vicinity of the channel region toproduce a corresponding strain in the channel region, which results in amodified mobility for electrons and holes, respectively. For example,creating tensile strain in the channel region increases the mobility ofelectrons, wherein, depending on the magnitude and direction of thetensile strain, an increase in mobility of 50% or more may be obtained,which, in turn, may directly translate into a corresponding increase inthe conductivity. On the other hand, compressive strain in the channelregion may increase the mobility of holes, thereby providing thepotential for enhancing the performance of P-type transistors. Theintroduction of stress or strain engineering into integrated circuitfabrication is an extremely promising approach for further devicegenerations, since, for example, strained silicon may be considered as a“new” type of semiconductor material, which may enable the fabricationof fast powerful semiconductor devices without requiring expensivesemiconductor materials, while many of the well-establishedmanufacturing techniques may still be used.

Consequently, it has been proposed to introduce, for instance, asilicon/germanium layer or a silicon/carbon layer in or below thechannel region to create tensile or compressive stress that may resultin a corresponding strain. Although the transistor performance may beconsiderably enhanced by the introduction of stress-creating layers inor below the channel region, significant efforts have to be made toimplement the formation of corresponding stress layers into theconventional and well-approved MOS technique. For instance, additionalepitaxial growth techniques have to be developed and implemented intothe process flow to form the germanium or carbon-containing stresslayers at appropriate locations in or below the channel region. Hence,process complexity is significantly increased, thereby also increasingproduction costs and the potential for a reduction in production yield.

Thus, in other approaches, external stress created by, for instance,overlaying layers, spacer elements and the like is used in an attempt tocreate a desired strain within the channel region. However, the processof creating the strain in the channel region by applying a specifiedexternal stress may suffer from an inefficient translation of theexternal stress into strain in the channel region. Hence, althoughproviding significant advantages over the above-discussed approachrequiring additional stress layers within the channel region, theefficiency of the stress transfer mechanism may depend on the processand device specifics and may result in a reduced performance gain forone type transistor.

In another approach, the hole mobility of PMOS transistors is enhancedby forming a strained silicon/germanium layer in the drain and sourceregions of the transistors, wherein the compressively strained drain andsource regions create uniaxial strain in the adjacent silicon channelregion. To this end, the drain and source regions of the PMOStransistors are selectively recessed, while the NMOS transistors aremasked, and the silicon/germanium layer is subsequently selectivelyformed in the PMOS transistor by epitaxial growth. Although thistechnique offers significant advantages in view of performance gain ofthe PMOS transistor and thus of the entire CMOS device, an appropriatedesign may have to be used that balances the difference in performancegain of the PMOS transistor and the NMOS transistor.

In view of the above-described situation, there exists a need for animproved technique that enables efficiently increasing the performanceof MOS transistors, while substantially avoiding or at least reducingone or more of the above-identified problems.

SUMMARY OF THE INVENTION

The following presents a simplified summary of the invention in order toprovide a basic understanding of some aspects of the invention. Thissummary is not an exhaustive overview of the invention. It is notintended to identify key or critical elements of the invention or todelineate the scope of the invention. Its sole purpose is to presentsome concepts in a simplified form as a prelude to the more detaileddescription that is discussed later.

Generally, the present invention is directed to a technique thatprovides an alternative or additional stress source for creating arespective strain in a transistor element, while avoiding at least someof the problems identified above. For this purpose, the isolationtrenches used in sophisticated semiconductor devices may be used toprovide, in whole or part, a desired high compressive stress. In otherillustrative embodiments, additionally or alternatively, an efficientstress engineering may be provided in which a different magnitude and/ortype of intrinsic stress in respective isolation trenches may begenerated. Since the trench isolation structure is located close to therespective transistor elements, an efficient stress transfer mechanismis provided, wherein, according to the present invention, a high degreeof compatibility with conventional process strategies may be maintained.

According to one illustrative embodiment of the present invention, amethod comprises forming a non-oxidizable layer within an isolationtrench formed in a semiconductor layer that is located above asubstrate. Moreover, the method comprises selectively modifying thenon-oxidizable layer within the isolation trench to generate compressivestress. Moreover, the isolation trench is filled with an insulatingmaterial and finally a transistor element is formed adjacent to theisolation trench, wherein the compressive stress induces a latticestrain in the transistor element.

According to another illustrative embodiment of the present invention, amethod comprises depositing a non-oxidizable layer having an intrinsicstress above a first isolation trench and a second isolation trench,wherein the first and the second isolation trenches are formed in asemiconductor layer. Furthermore, the intrinsic stress in the firstisolation trench is selectively modified and the first and secondisolation trenches are then filled with an insulating material.

In accordance with yet another illustrative embodiment of the presentinvention, a semiconductor device comprises a first isolation trenchformed in a semiconductor layer and having sidewalls and a bottom side.An insulating liner material is formed on the sidewalls on the bottomside, wherein the insulating liner material comprises silicon, nitrogenand oxygen and has a compressive intrinsic stress. Finally, thesemiconductor device comprises an insulating oxide material formedadjacent to the insulating liner material to fill the isolation trench.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be understood by reference to the followingdescription taken in conjunction with the accompanying drawings, inwhich like reference numerals identify like elements, and in which:

FIGS. 1 a-1 f schematically show cross-sectional views of asemiconductor device during the formation of an isolation trench havinga compressive stress in accordance with illustrative embodiments of thepresent invention;

FIG. 2 schematically illustrates a cross-sectional view of asemiconductor device during the formation of an isolation trench bymeans of a liner material having an intrinsic stress; and

FIGS. 3 a-3 d schematically illustrate cross-sectional views of asemiconductor device having differently stressed isolation trenchesduring various manufacturing stages in accordance with yet otherillustrative embodiments of the present invention.

While the invention is susceptible to various modifications andalternative forms, specific embodiments thereof have been shown by wayof example in the drawings and are herein described in detail. It shouldbe understood, however, that the description herein of specificembodiments is not intended to limit the invention to the particularforms disclosed, but on the contrary, the intention is to cover allmodifications, equivalents, and alternatives falling within the spiritand scope of the invention as defined by the appended claims.

DETAILED DESCRIPTION OF THE INVENTION

Illustrative embodiments of the invention are described below. In theinterest of clarity, not all features of an actual implementation aredescribed in this specification. It will of course be appreciated thatin the development of any such actual embodiment, numerousimplementation-specific decisions must be made to achieve thedevelopers' specific goals, such as compliance with system-related andbusiness-related constraints, which will vary from one implementation toanother. Moreover, it will be appreciated that such a development effortmight be complex and time-consuming, but would nevertheless be a routineundertaking for those of ordinary skill in the art having the benefit ofthis disclosure.

The present invention will now be described with reference to theattached figures. Various structures, systems and devices areschematically depicted in the drawings for purposes of explanation onlyand so as to not obscure the present invention with details that arewell known to those skilled in the art. Nevertheless, the attacheddrawings are included to describe and explain illustrative examples ofthe present invention. The words and phrases used herein should beunderstood and interpreted to have a meaning consistent with theunderstanding of those words and phrases by those skilled in therelevant art. No special definition of a term or phrase, i.e., adefinition that is different from the ordinary and customary meaning asunderstood by those skilled in the art, is intended to be implied byconsistent usage of the term or phrase herein. To the extent that a termor phrase is intended to have a special meaning, i.e., a meaning otherthan that understood by skilled artisans, such a special definition willbe expressly set forth in the specification in a definitional mannerthat directly and unequivocally provides the special definition for theterm or phrase.

Generally, the present invention is based on the concept that efficientstrain engineering may be achieved by using stress produced inrespective isolation trenches as an efficient stress source. Due to theever decreasing feature sizes of advanced semiconductor devices,transistor elements may be located close to the respective trenchisolations so that any increased stress created by the isolationtrenches may be advantageously used in creating a respective strain inthe channel region of the transistor element, thereby improving theperformance thereof, as is discussed above. It should be appreciatedthat the principles of the present invention as have been pointed outabove and as will be discussed in more detail later on may beadvantageously applied to any specific device architecture, includingthe formation of transistor elements in bulk semiconductor substrates.The present invention is highly advantageous in the context ofsilicon-on-insulator (SOI) architectures, since here typically theisolation trenches extend down to the buried insulating layer, therebyproviding the potential for creating a desired stress that may becontinuously transferred along the entire depth of the transistor activeregion and even along the interface of the active region and the buriedinsulating layer. Consequently, even in highly sophisticatedapplications, in which in some cases the interface between the activeregion and the buried insulating layer may also serve as a channelregion, an efficient stress transfer may be accomplished. For thispurpose, the present invention employs process techniques that may notunduly contribute to process complexity so as to still provide a highdegree of compatibility to existing conventional manufacturingtechniques.

With reference to FIGS. 1 a-1 f, 2 and 3 a-3 d, further illustrativeembodiments of the present invention will now be described in moredetail. FIG. 1 a schematically shows a cross-sectional view of asemiconductor device 100 comprising a substrate 101, which may representany appropriate carrier for receiving or having formed therein anappropriate semiconductor layer 103, such as a silicon layer, asilicon/germanium layer and the like. In one illustrative embodiment,the semiconductor layer 103 may represent a silicon-based semiconductorlayer having a thickness that is appropriate for the formation of fullyor partially depleted SOI transistor elements therein. It should beappreciated that a silicon-based semiconductor layer is to be understoodas a crystalline semiconductor layer including a significant amount ofsilicon, while other materials, such as germanium, carbon or othersemiconductor materials, may also be incorporated therein. For example,a semiconductor layer comprising 50 atomic percent or more silicon maybe considered as a silicon-based semiconductor layer.

In one illustrative embodiment, the semiconductor device 100 comprises aburied insulating layer 102 on which may be formed the semiconductorlayer 103 so as to form an SOI architecture. The buried insulating layer102 may be comprised of any appropriate material, such as silicondioxide, silicon nitride or a combination thereof, or any other suitabledielectric materials. An isolation trench 105 is formed in thesemiconductor layer 103 and extends, in one illustrative embodiment,down to the buried insulating layer 102, thereby defining asemiconductor region 110 in the layer 103, which may be bordered by theisolation trench 105. Moreover, at this manufacturing stage, thesemiconductor device 100 comprises a layer 104 comprised of anon-oxidizable material, which is formed on exposed surface portions ofthe device 100 and thus on sidewalls 105S and a bottom 105B of theisolation trench 105. In one illustrative embodiment, the layer 104 maybe comprised of silicon nitride, whereas, in other illustrativeembodiments, other materials, such as silicon carbide and the like, maybe used. A thickness of the layer 104 may be appropriately selected withrespect to the trench dimensions and in view of the stoppingcharacteristics of the layer 104 in a subsequent chemical mechanicalpolishing (CMP) process for removing any excess material that has to befilled into the isolation trench 104 in a later manufacturing stage. Forexample, the layer 104 may have a thickness of approximately 5-50 nm,depending on the device requirements.

A typical process flow for forming the semiconductor device 100 as shownin FIG. 1 a may comprise the following processes. After providing thesubstrate 101 having formed thereon the semiconductor layer 103, or byforming the semiconductor layer 103 above the substrate 101, forinstance by well-established wafer bond techniques when an SOIarchitecture is considered, or by epitaxial growth techniques, aphotolithography process may be performed on the basis ofwell-established recipes to provide an appropriate resist mask or hardmask (not shown) on the basis of which an etch process may be performedin order to etch through the semiconductor layer 103, wherein, in someillustrative embodiments, the etch process may stop in or on the buriedinsulating layer 102. Appropriate etch techniques for the formation ofthe isolation trench 104 are well established in the art. After the etchprocess and removal of any mask layers, such as a resist mask, the layer104 may be deposited, wherein, in one illustrative embodiment,well-established chemical vapor deposition (CVD) techniques on the basisof a low pressure ambient may be used in order to form a silicon nitridelayer having the desired thickness. In other illustrative embodiments,as will be discussed later on, other appropriate deposition techniquesmay be used, such as plasma enhanced chemical vapor deposition (PECVD)in order to provide the layer 104 with an intrinsic mechanical stress onthe basis of suitably controlling certain deposition parameters.

FIG. 1 b schematically shows the semiconductor device 100 at a furtheradvanced manufacturing stage, in which a mask 106, such as a resistmask, may be formed above the device 100 in such a manner that at leastthe isolation trench 105 is exposed. In other illustrative embodiments,the resist mask 106 may be omitted at this manufacturing stage or theresist mask 106 may be designed such that at least other isolationtrenches may be covered, for which the intrinsic stress provided by thelayer 104 is not to be modified, as will be discussed later on in moredetail. Omitting the resist layer 106 in this manufacturing stage maylead to a common treatment of any exposed isolation trench provided inthe device 100. Moreover, the device 100 as shown in FIG. 1 b issubjected to a surface treatment 107 on the basis of an ion bombardmentwhich, in one illustrative embodiment, may be established by performingan ion implantation process. For this purpose, any appropriate ionspecies may be used, such as inert species in the form of noble gasions, or nitrogen, silicon, germanium and the like. It should beappreciated that appropriate process parameters, such as dose andimplantation energy when the treatment 107 is carried out in the form ofan ion implantation, may be readily established on the basis of testruns, simulation and the like. In some illustrative embodiments, whenthe mask 106 may not be provided, process parameters of the treatment107, such as implantation energy, may be selected such that undue damageof the underlying semiconductor region 110 may be substantially avoided.In other illustrative embodiments, any implantation-induced damage thatmay be caused in the semiconductor region 110 may be re-crystallized ina later phase during a high temperature processing, for instance duringthe densification of an insulating material to be filled into theisolation trench 105.

During the treatment 107, exposed portions 104B of the layer 104, whichmay extend horizontally beyond the isolation trench 105, orsubstantially the whole layer 104 may be represented by the exposedportion 104B, may be modified in their crystalline structure, wherein,in the case of a silicon nitride layer, a significant amount of siliconand nitrogen bonds are destroyed, thereby significantly affecting themechanical characteristics of the exposed layer portions, whereinprocess parameters may be selected to effect the modification up to anydesired depth including the total thickness of the portion 104B. Hence,the exposed portion of the layer 104 may be made porous to a certaindegree, thereby providing the potential for providing additionaldiffusion paths during a subsequent treatment to increase thecompressive stress of the exposed layer portion.

FIG. 1 c schematically shows the semiconductor device 100 after theremoval of the mask 106, if provided, and during a further treatment108, which may be performed in an oxidizing ambient. In one illustrativeembodiment, the ambient 108 may be established on the basis of oxygenand/or ozone at elevated temperatures in the range of approximately500-1100° C., when the duration of the treatment 108 may be based on therequired amount of oxide formation. For example, a duration of severalseconds to several hours may be used, wherein a target treatment timemay be readily determined on the basis of test results of testsubstrates and/or product substrates. In still other illustrativeembodiments, the ambient 108 may be established on the basis of aplasma, wherein additionally a high degree of directionality of oxygenor ozone ions may be achieved, thereby potentially enhancing theeffectiveness of oxygen diffusion into the previously modified portionof the layer 104. During the diffusion of oxygen into the modifiedportion of the layer 104 and based on the elevated temperature, theoxygen may readily react with free silicon provided by the previoustreatment 107, thereby building up an increasing amount of silicondioxide in the exposed layer portion of the layer 104 and thus forming aportion 104A having an increased compressive stress due to the increasedvolume of silicon dioxide compared to silicon. It should be appreciatedthat, in the embodiments shown, the increased oxygen diffusion issubstantially restricted to the exposed portions previously treated bythe treatment 107, since non-treated portions may still have a highdegree of structural integrity, thereby significantly reducing orsubstantially preventing any oxygen diffusion during the treatment 108in the oxidizing ambient. For example, silicon nitride may efficientlyblock oxygen diffusion even at very high temperatures. In otherillustrative embodiments, when significant portions of the layer 104 mayhave been exposed to the treatment 107, or when the mask 106 hascompletely been omitted during the preceding treatment 107, thecorresponding oxygen diffusion may also occur in horizontal portions ofthe layer 104.

FIG. 1 d schematically shows the semiconductor device 100 after thecompletion of the treatment 108 in the oxidizing ambient so that theexposed portion 104A now comprises a significant compressive stress 109,which may then be highly efficiently transferred into the semiconductorregion 110. It should be appreciated that the resulting compressivestress 109 is also efficiently transferred into the buried insulatinglayer 102, thereby also transferring a respective compressive stressinto the buried insulating layer 102 located below the semiconductorregion 110. A corresponding stress transfer mechanism may be highlyadvantageous in the context of highly sophisticated fully or partiallydepleted transistor devices, wherein charge carrier transport may alsotake place at an interface between the region 110 and the buriedinsulating layer 102, when a transistor is formed in the region 110.

FIG. 1 e schematically shows the semiconductor device 100 in a furtheradvanced manufacturing stage. The isolation trench 105 is filled with aninsulating material 111, which in one illustrative embodiment is silicondioxide, thereby providing a high degree of compatibility withconventional process techniques. The insulating material 111 may bedeposited on the basis of any appropriate technique, such as CVD on thebasis of TEOS or any other deposition regime. During the depositionprocess, excess material may be provided to reliably fill the isolationtrench 105. Thereafter, the excess material may be removed by anyappropriate planarization technique, such as chemical mechanicalpolishing (CMP), wherein the layer 104, i.e., horizontal portionsthereof, may serve as a CMP stop layer to reliably control the removalof the excess material of the insulating material 111. For theembodiments illustrated in FIGS. 1 a-1 d, the structural integrity ofthe layer 104 as deposited may have been maintained at the horizontalportions, thereby substantially not affecting the respectivecharacteristics during the CMP process. In other embodiments, whensignificant portions of the layer 104 may have experienced the treatment107 and may thus have included therein a significant amount of silicondioxide, the stopping characteristics of the layer 104 may be lesspronounced, while a significant difference with respect to theinsulating material 111 may nevertheless provide a high degree ofcontrollability in the CMP process.

Prior to or after the CMP process, a heat treatment may be performed toimpart an increased density to the insulating material 111, while, inother embodiments, a corresponding densification may be omitted. In oneembodiment, the heat treatment for densifying the insulating materialmay be carried out in an oxidizing ambient, thereby further increasingthe oxygen diffusion into the portion 104A, which may result in afurther increased compressive stress. After the CMP process, theremaining portion of the layer 104 outside the isolation trench 105 maybe removed on the basis of a selective etch process, which may be basedon hot phosphoric acid, when the layer 104 outside the isolation trench105 may have not been treated during the process 107 and when the layer104 is substantially comprised of silicon nitride. In this case, theinitial characteristics of the silicon nitride layer are substantiallymaintained and thus the layer 104 may be efficiently removed bywell-established recipes with hot phosphoric acid. During this selectiveetch process, the modified portion 104A may exhibit a reduced etch ratedue to the increased amount of silicon dioxide contained therein, sothat undue erosion of the material of the portion 104A may be reduced ormay be substantially suppressed. Consequently, a highly reliableisolation trench 105 is provided, wherein the magnitude of thecompressive stress 109 may be adjusted on the basis of processparameters regarding the treatments 107 and 108 and possibly a heattreatment for densifying the insulating material 111.

FIG. 1 f schematically shows the semiconductor device 100 in a furtheradvanced manufacturing stage, wherein a transistor element 120 is formedin and above the semiconductor region 110. The transistor 120 maycomprise a channel region 112, which may have a strained crystallinestructure due to a strain 113 caused by the high compressive stress 109provided by the isolation trench 105. For example, the transistor 120may represent, in one illustrative embodiment, a P-channel transistor sothat the compressive strain 113 may positively influence the carriermobility of the holes in the channel region 112, thereby improving thetransistor performance.

FIG. 2 schematically shows a cross-sectional view of a semiconductordevice 200 in accordance with further illustrative embodiments, whereina respective insulating liner may be formed on the basis of a depositiontechnique that enables the creation of a high magnitude of intrinsicstress. The device 200 comprises a substrate 201, above which is formeda semiconductor layer 203, wherein, in illustrative embodiments, aburied insulating layer 202 may be provided between the substrate 201and the layer 203. Furthermore, an isolation trench 205 is formed in thelayer 203, thereby bordering a semiconductor region 210, in and overwhich respective transistor elements are to be formed. Regarding theindividual components 201, 202, 203 and 210, the same criteria apply aspreviously explained with reference to the device 100. Furthermore, alayer 204 is formed above the semiconductor layer 203 and within theisolation trench 205. The layer 204 may be comprised of silicon nitride,which may be formed on the basis of a PECVD process 214, in whichprocess parameters, such as pressure, temperature, plasma power, biaspower for adjusting a directionality of ions in the ambient of theprocess 214 and the like, may be appropriately controlled to provide thelayer 204 with a desired type and magnitude of intrinsic stress. Siliconnitride may be efficiently deposited with a high amount of compressiveor tensile stress with a magnitude ranging up to 1.5 GPa (GigaPascal) byappropriately selecting the deposition parameters specified above. Thus,in one illustrative embodiment, the layer 204 may be deposited toexhibit a high compressive stress 209, whereas, in other illustrativeembodiments, the layer 204 may be provided with tensile stress.

In some illustrative embodiments, an additional CMP stop layer (notshown) may be provided prior to forming the isolation trench 205, whenthe deposition process 214 may be considered inappropriate for providinga required high degree of conformity to establish a desired degree ofthickness conformity on horizontal portions of the layer 203. Forexample, the additional CMP stop layer may have an even highermechanical integrity, when for instance provided as silicon carbide,compared to silicon nitride, thereby providing the possibility toreliably remove excess material of the layer 204 by CMP, which may thenbe controlled on the basis of the additional CMP stop layer. In otherillustrative embodiments, the thickness uniformity achieved by thedeposition process 214 at least at the horizontal surface portions ofthe device 200 may be considered appropriate to provide reliable CMPcontrol, wherein the remaining excess material of the layer 204 may thenbe removed by an appropriate selective etch process in conformity with aprocess sequence as previously described with reference to the device100.

Thereafter, the further processing may be continued as is describedabove, i.e., the isolation trench 205 may be filled with an appropriateinsulating material, such as silicon dioxide, and further processing maybe continued by removing any excess material which, as previouslyexplained, may be based on an additional CMP stop layer, or which may beperformed on the basis of the layer 204 as deposited. Thereafter, atransistor element may be formed in and above the region 210, whereinthe high compressive stress 209 also provides a corresponding transistorperformance as is also described with reference to the transistor 120.Similarly, the layer 204 may be formed with a high intrinsic tensilestress in order to provide a respective tensile stress to the region210, depending on process and device requirements.

With reference to FIGS. 3 a-3 c, further illustrative embodiments of thepresent invention will now be described in more detail, in which adifferent type or magnitude of intrinsic stress may be provided bydifferent isolation trenches.

In FIG. 3 a, the semiconductor device 300 comprises a substrate 301,above which is formed a semiconductor layer 303, wherein, inillustrative embodiments, a buried insulating layer 302 may be formedbetween the substrate 301 and the layer 303. With respect to specificsof the components 301, 302, 303, it is referred to the correspondingcomponents as described with reference to FIGS. 1 a-1 f. The device 300further comprises a first isolation trench 305A and a second isolationtrench 305B, which respectively define a first semiconductor region 310Aand a second semiconductor region 310B. Moreover, a layer 304 is formedabove the semiconductor layer 303 and within the first and secondisolation trenches 305A, 305B. The layer 304 may be comprised of anon-oxidizable material, which in one illustrative embodiment isrepresented by silicon nitride. In one embodiment, the layer 304 mayhave an intrinsic stress, such as tensile or compressive stress of adesired magnitude. For example, the layer 304 may have a relatively lowmagnitude of intrinsic stress, while in other embodiments a moderatelyhigh magnitude of intrinsic stress may be provided, depending on thefurther process strategy. Furthermore, the semiconductor device 300 maybe covered by a mask layer 306, which may expose the first isolationtrench 305A while covering the second isolation trench 305B.

The device 300 as shown in FIG. 3 a may be formed in accordance withsubstantially the same processes as are previously described withreference to the device 100. Moreover, it should be appreciated that,depending on the desired type and magnitude of intrinsic stress of thelayer 304, any appropriate deposition technique may be used. Forexample, in some illustrative embodiments, the PECVD technique describedwith reference to FIG. 2, i.e., the process 214, may be used to form thelayer 304 having a high tensile or compressive stress, depending onprocess and device requirements. In still other illustrativeembodiments, low pressure chemical vapor deposition (LPCVD) techniquesmay be used in accordance with well-established recipes. Thereafter, themask 306, for instance in the form of a resist mask, may be formed onthe basis of well-established photolithography techniques. Thereafter,the device 300 may be subjected to a treatment 307, which in oneembodiment may represent an ion bombardment to modify the exposedportion of the layer 304 within the first isolation trench 305A. Thatis, a similar treatment as the treatment 107 may be performed, therebyreducing the mechanical integrity of the exposed layer portion in thefirst isolation trench 305A. Depending on the initial characteristics ofthe layer 304, any intrinsic stress contained therein may besignificantly relaxed due to the treatment 307. For example, if thelayer 304 is initially provided with a high magnitude of compressive ortensile stress, a significant stress relaxation may be obtained by thetreatment 307.

FIG. 3 b schematically shows the semiconductor device 300 after thecompletion of the treatment 307 and the removal of the mask 306.Moreover, the device 300 may be exposed to an oxidizing ambient 308 atelevated temperatures, wherein the ambient 308 may be similar to theambient 108 previously described. During the treatment 308, previouslyexposed portions in the first isolation trench 305A may be furthermodified to form a modified portion 304A, in which, for instance, anincreased amount of oxygen may be incorporated into the layer portion304A, thereby providing increased compressive stress, as is previouslyexplained. In other illustrative embodiments, the semiconductor device300 may not be subjected to the treatment 308 when the layer 304 isinitially provided with a high intrinsic stress and the stressrelaxation obtained by the treatment 307 is considered appropriate forthe stress engineering within the semiconductor region 310A adjacent tothe first isolation trench 305A. It should be appreciated that similarlyto the treatment 108, also in this case the previously modifiedportions, which were not exposed to the treatment 307, may substantiallymaintain their initial mechanical integrity and thus their initialstress characteristics. Consequently, the second isolation trench 305Bmay have a substantially non-modified portion 304B.

FIG. 3 c schematically illustrates the semiconductor device 300 in afurther advanced manufacturing stage, in which the first and secondisolation trenches 305A, 305B are filled with an appropriate insulatingmaterial 311, such as silicon dioxide, which may have been deposited onthe basis of well-established recipes followed by the removal of anyexcess material, thereby planarizing the topography of the device 300,wherein the layer 304 may also act as a CMP stop layer, as previouslydescribed. Consequently, the first isolation trench 305A may have a highcompressive stress 309A acting on the adjacent semiconductor region310A. Similarly, the second isolation trench 305B may exhibit, in someillustrative embodiments, a substantially low intrinsic stress dependingon the initial stress characteristics of the layer 304 or, in otherillustrative embodiments, even a moderately high tensile stress 309B maybe exerted to the adjacent semiconductor region 310B, when the initiallayer 304 has been deposited so as to exhibit a high tensile stress.

FIG. 3 d schematically shows the semiconductor device 300 in a furtheradvanced manufacturing stage, in which a first transistor element 320Ais formed in and on the first semiconductor region 310A, while a secondtransistor 320B is formed in an on the second semiconductor region 310B.Consequently, a respective stress transfer from the first isolationtrench into a channel region 312A of the first transistor 320A may beachieved, thereby inducing a first strain 313A in the channel region312A. Similarly, a different type or magnitude of strain 313B may beinduced in the channel region 312B of the second transistor element320B. For example, when the first strain 313A is a compressive strain,the first transistor may represent a P-channel transistor. Similarly,when the second strain 313B is a reduced compressive strain or a tensilestrain, the second transistor 320B may represent an N-channeltransistor.

As a result, the present invention provides an efficient strain-inducingmechanism on the basis of a stress engineering technique applied toisolation trenches, wherein, in advanced applications requiring SOIarchitectures, a highly efficient stress transfer may be accomplished byproviding respectively designed liner materials in the isolationtrenches. For this purpose, the characteristics of a non-oxidizablelayer may be efficiently modified to incorporate a significant amount ofsilicon dioxide, thereby providing the potential for generating a highcompressive stress in a highly controllable fashion. In otherillustrative embodiments, additionally or alternatively, the linermaterial may be deposited to exhibit a high intrinsic stress, whereinthe type and the magnitude may be substantially determined on the basisof deposition parameters. Thereafter, the intrinsic stress may beselectively modified or even enhanced to provide an increased degree ofdesign and process flexibility. For example, compressive stress may begenerated in the vicinity of P-channel transistors, while, in someillustrative embodiments, additionally, tensile stress or a reducedcompressive stress may be created adjacent to N-channel transistors,thereby significantly enhancing the performance thereof As aconsequence, a highly efficient strain-inducing mechanism is provided,wherein, in advanced SOI architectures, the stress transfer may beobtained over the entire depth of the respective semiconductor layer.Moreover, the enhanced stress engineering techniques of the presentinvention based on modifying a liner material of isolation trenches maybe efficiently combined with other stress engineering techniquespreviously discussed.

The particular embodiments disclosed above are illustrative only, as theinvention may be modified and practiced in different but equivalentmanners apparent to those skilled in the art having the benefit of theteachings herein. For example, the process steps set forth above may beperformed in a different order. Furthermore, no limitations are intendedto the details of construction or design herein shown, other than asdescribed in the claims below. It is therefore evident that theparticular embodiments disclosed above may be altered or modified andall such variations are considered within the scope and spirit of theinvention.

Accordingly, the protection sought herein is as set forth in the claimsbelow.

1-19. (canceled)
 20. A static RAM cell, comprising: a select transistorconfigured to receive at least one of a read signal and a write signal;and a first field effect transistor comprising a first body regionconnected to said select transistor so as to enable selectiveapplication of said at least one of a read signal and a write signal tosaid first body region.
 21. The static RAM cell of claim 20, furthercomprising a second field effect transistor connected to said firstfield effect transistor, said first and second field effect transistorsforming a flip flop circuit for data storage.
 22. The static RAM cell ofclaim 21, wherein said flip flop circuit comprises an input forreceiving said read signal and said write signal.
 23. The static RAMcell of claim 21, wherein said flip flop circuit comprises an inputconnected to said first body region and an output connect to a gateelectrode of said first field effect transistor.
 24. The static RAM cellof claim 20, wherein said first field effect transistor comprises: adrain region and a source region having a first conductivity type; saidfirst body region having a second conductivity type that is other thansaid first conductivity type; and a doped region located between saiddrain region and said source region, wherein said doped region has saidfirst conductivity type.
 25. The static RAM cell of claim 24, furthercomprising a second field effect transistor coupled to said first fieldeffect transistor, said second field effect transistor comprising asecond body region having said first conductivity type and a seconddoped region comprising said second conductivity type.
 26. The staticRAM cell of claim 23, wherein said output is connected a drain of saidfirst field effect transistor and a gate electrode of said second fieldeffect transistor.
 27. The static RAM cell of claim 26, wherein saidinput is connected to a drain of said second field effect transistor.28. The static RAM cell of claim 27, wherein said second field effecttransistor comprises a second body region coupled to a source of saidsecond field effect transistor.
 29. The static RAM cell of claim 20,wherein the select transistor is coupled to a bit line for receivingsaid at least one read or write signal, further comprising a secondfield effect transistor connected to said first field effect transistor,said first and second field effect transistors forming a flip flopcircuit for data storage, wherein said flip flop circuit comprises aninput/output terminal connected to said first body region and a drain ofsaid second field effect transistor.
 30. The static RAM cell of claim29, wherein a gate of said first field effect transistor, a gate of saidsecond field effect transistor, and a drain of said second field effecttransistor are coupled together.
 31. The static RAM cell of claim 30,wherein said second field effect transistor comprises a second bodyregion coupled to a source of said second field effect transistor.